In the field of microprocessors, interruptions are events that occur during instruction processing, causing the flow control to be passed to an interruption handling routine. In the process, certain processor state information is saved automatically by the hardware which normally resides on the same integrated circuit as the central processing unit (CPU). Upon completion of interrupt processing, a "return from interruption" is executed, which restores the saved processor state, an execution proceeds from the interruption instruction. Every complex computer system includes some sort of mechanism for dealing with interruptions.
In the past, small computers based upon the popular i386 and i486 microprocessors typically had no need to be concerned with interprocessor interrupt communications. These systems were intended to communicate via a system bus, but the system bus could not be used for interprocessor interrupt communications because the bus architecture needed to maintain backward compatibility with the older x86 platform. This situation, for example, led to the development of a separate bus, dedicated bus designed to handle the function of interprocessor interrupt communications without disturbing the existing platform or interfering with backward compatibility. By way of example, this approach is disclosed in U.S. Pat. No. 5,511,200 which is assigned to the assignee of the present application.
Other approaches to the problem of interrupt handling include U.S. Pat. No. 4,495,569, which teaches a multiprocessor system with an interrupt controller for applying an interrupt to a destination processor. A bus interface interrupt arrangement which provides separate interrupt controllers for each bus in a multi-bus computer system is disclosed in U.S. Pat. No. 5,134,706. Yet another approach to the problem is taught in U.S. Pat. No. 5,155,853 which describes an interrupt controller integrated with a CPU. The interrupt controller unit responds to interrupt request signals and starts an interrupt handling routine.
In multiprocessor systems based upon the Intel Architecture.TM., the use of a dedicated processor interrupt control (PIC) bus gained popularity. Consequently there developed an entire protocol for governing the operation of the PIC bus. For instance, certain features were created in the multiprocessor system environment which were quickly adopted by software developers. One such feature was the arbitration concept of a lowest priority destination (LPD). According to the LPD arbitration scheme, an interrupt generated within the multiprocessor system gets transferred to the least busy processor (i.e., the lowest priority processor) for interrupt handling. In other words, the least busy processor in the system is identified according to the LPD scheme, and that processor is then given the task of handling interrupts. Note that priority in such a system is dynamic, that is, a processor may be extremely busy at one moment (i.e., highest priority) and idle the next moment.
The success of the PIC architecture led to its inclusion in multiprocessor systems based upon the Pentium.RTM. and Pentium.RTM. PrO.TM. multiprocessor computer systems. Both processors have been designed to be compatible with a PIC bus.
One of the problems that has developed as CPU frequency continues to increase and power supply potentials decrease, is that the limitations inherent in the PIC bus architecture have become evident. To be specific, the PIC bus architecture has certain electrical requirements for voltage swings, operating frequencies, voltage potentials, etc., that are not compatible with more advanced, high frequency, low power multiprocessor systems. As studied another way the electrical nature of the PIC bus is limited by its dependence upon over voltage level requirements which are not compatible with more modern multiprocessor system designs. The challenge facing system designers is how to incorporate hardware enhancements without sacrificing software compatibility such as lowest priority processor targeting which is needed for x86 compatibility. In other words, the added enhancements in hardware and software for future microprocessor systems mandates departure from the traditional PIC bus architecture. But at the same time, future processor proliferations must support PIC bus architectural features, such as targeting lowest priority processor, to achieve full binary compatibility with existing software.
As will be seen, the present invention provides a mechanism for emulation of lowest priority processor in a multiprocessor system in which interprocessor interrupts are communicated across a high speed system bus.